Bump structure for a semiconductor device and method of manufacture

ABSTRACT

A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive.

BACKGROUND OF THE INVENTION

A number of different techniques exist for providing electricalconnection between a semiconductor chip or package and a circuit boardor other substrate. The current trend in many of these techniques is theuse of solder bumps to form electrical connections instead of wirebonding. For example, bumps are used in such techniques as tape carrierpackage (TCP), chip on film (COF), and chip on glass (COG). Oftentechniques such as TCP and COF are more broadly referred to as tapeautomated bonding (TAB).

While bumps provide an advantage over wire bonding by allowing for areduction in the spacing between the solder bumps as compared to thespacing between wire bonds, even bump techniques face potentiallimitations on the spacing between the bumps. For example, in the COGtechnique, a semiconductor chip (e.g., a liquid crystal display (LCD)driver integrated circuit (IC) package) may be bonded directly to theLCD substrate. In this technique, ACF (anisotropic conductive film) tapeis disposed between pads of the LCD substrate and the associated bumpson the driver IC package to form the electrical connection. ACF tapecontains electrically conductive particles that are embedded in aninsulating material. The conductive particles provide electricalconnection between the solder bumps and the pads on the LCD substrate.As the gap between bumps, however, becomes smaller, the particles in theACF tape may provide electrical connection between bumps; thus, causinga short circuit.

SUMMARY OF THE INVENTION

The present invention provides a bump structure that removes barriers onthe spacing between solder bumps of semiconductor chips or packages. Assuch, the present invention allows for smaller and thinner semiconductordevices.

In one exemplary embodiment, a plurality of bump structures are arrayedalong a substrate in a first direction. Each bump structure has a widthin the first direction greater than a pitch gap between successivelyarrayed bump structures. The pitch gap may be thought of as a gapmeasured at the substrate along the first direction between planes offacing sidewalls of the successively arrayed bump structures. At leastone bump structure has a sidewall facing in the first direction that isnon-conductive. Because the sidewall is non-conductive, conductiveparticles disposed between this bump and the bump adjacent to thenon-conductive sidewall should not form a short circuit between the twobumps.

In one exemplary embodiment, each bump structure has at least onenon-conductive sidewall facing in the first direction.

In another exemplary embodiment, each bump structure has two oppositelyfacing non-conductive sidewalls facing in the first direction.

In a further exemplary embodiment, each bump structure has onenon-conductive sidewall facing in the first direction and one conductivesidewall facing in the first direction such that the conductive sidewalldoes not face the conductive sidewall of another bump structure.

In a still further exemplary embodiment, the array of bump structuresalternate from a first type to a second type. The bump structure of thefirst type has two oppositely facing non-conductive sidewalls that facein the first direction, and the bump structure of the second type hastwo oppositely facing conductive sidewalls that face in the firstdirection.

In association with any of the above described embodiments, thesuccessively arrayed bump structures may be disposed offset from oneanother in a second direction along the substrate.

An exemplary embodiment,of the, present invention also includes aplurality of bumps arrayed along a substrate in a first direction and aplurality of conductive lines formed in a second direction. Eachconductive line is associated with one of the bumps, and each conductiveline is disposed over a top surface of the associated bump and over twooppositely facing sidewalls of the bump; the two oppositely facingsidewalls facing in the second direction. Each conductive line extendsover the substrate from each of the two oppositely facing sidewalls.Because of this, the conductive line assists in maintaining theassociated bump adhered to the substrate.

Other exemplary embodiments of the present invention provide for methodsof forming the above described embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given herein below and the accompanying drawings,wherein like elements are represented by like reference numerals, whichare given by way of illustration only and thus are not limiting of thepresent invention and wherein:

FIG. 1 illustrates a semiconductor device having a bump structureaccording to an exemplary embodiment of the present invention;

FIG. 2 illustrates a cross-section of the substrate shown in FIG. 1along line II-II;

FIG. 3 illustrates a cross-section of the substrate shown in FIG. 1along line III-III;

FIG. 4 illustrates a semiconductor device having a bump structureaccording to an exemplary embodiment of the present invention;

FIG. 5 illustrates a cross-section of the semiconductor device shown inFIG. 4 along line V-V;

FIG. 6 illustrates a semiconductor device having a bump structureaccording to an exemplary embodiment of the present invention;

FIG. 7 illustrates a cross-section of the semiconductor device shown inFIG. 6 along line VII-VII;

FIG. 8 illustrates a semiconductor device having a bump structureaccording to an exemplary embodiment of the present invention.

FIG. 9 illustrates a top down view of a semiconductor device havingthree groups of bump structures;

FIGS. 10A-15B illustrate an embodiment of a method of fabricating a bumpstructure according to the present invention where FIGS. 10A, 11A, 12,13A, 14 and 15A represent cross-sectional views of the substrate duringthe fabrication process, and FIGS. 10B, 11B, 13B and 15B represent topdown views of the substrate during the fabrication process.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The present invention provides a bump structure that removes barriers onthe spacing between solder bumps of semiconductor chips or packages. Assuch, the present invention allows for smaller and thinner semiconductordevices. First, several structual embodiments according to the presentinvention will be described followed by a description of a method forforming a bump structure according to the present invention.

First Structural Embodiment

FIG. 1 illustrates a semiconductor device having a bump structureaccording to an exemplary embodiment of the present invention. As shown,bump structures 100 are arrayed on an insulating layer 202 over asubstrate 200 in a first direction indicated by a double headed arrow A.Each bump structure 100 includes a non-conductive bump 102. Thenon-conductive bump 102 has two oppositely facing sidewalls 104 thatface in the first direction and two oppositely facing sidewalls 106 thatface in a second direction, substantially perpendicular to the firstdirection, indicated by a double headed arrow B.

In one example embodiment, each bump 102 has a height H of 2 to 30 um, awidth Wb of 10 to 50 um and a length of 20 to 200 um.

Each bump structure 100 also includes a conductive layer 108 disposedover a top surface of an associated bump 102 and each sidewall 106facing in the second direction. The conductive layer 108 on the bump 102forms part of a conductive line 110 that extends a shorter distance overthe substrate 200 from one sidewall 104, and extends a longer distanceover the substrate 200 from the other sidewall 104. As shown, theconductive line 110 extends in the second direction. The longerextension of the conductive line 110 leads to an associated chip pad 204where the conductive layer 110 is electrically connected to theassociated pad 204. As will be appreciated the pad 204 provideselectrical connection between the conductive line 110 and circuitry (notshown) formed on the substrate 200.

FIG. 2 illustrates a cross-section of the substrate shown in FIG. 1along line II-II and FIG. 3 illustrates a cross-section of the substrateshown in FIG. 1 along line III-III. While not shown in FIG. 1 for thepurposes of clarity, the bump structure according to this embodiment ofthe present invention further includes a passivation layer 180 formedover portions of the substrate 200 as shown in FIGS. 2 and 3.

FIG. 2 shows the pitch gap PG between consecutive bump structures 100 inFIG. 1. The pitch gap PG is the distance between two bump structures;and more particularly, may be the gap as measured at the substrate 200or passivation layer 180 along the first direction between the planes inwhich facing sidewalls 104 of the successively arrayed bump structures100 lie. In this embodiment, the width Wb of the bump structure 100 isgreater than the pitch gap PG. For example, the pitch gap PG may beabout 10 um.

Because the pitch gap PG is less than the width WBb of the bumpstructure 100, a short circuit when using, for example, an ACF tapemight be expected. However, because the sidewalls 104 of the bumpstructures 100 facing in the first direction are non-conductive, suchshort circuits are prevented. Consequently, the present inventionprovides a bump structure that removes barriers on the spacing betweensolder bumps of semiconductor chips or packages. As such, the presentinvention allows for smaller and thinner semiconductor devices.

Second Structural Embodiment

FIG. 4 illustrates a semiconductor device having a bump structureaccording to an exemplary embodiment of the present invention, and FIG.5 illustrates a cross-section of the semiconductor device shown in FIG.4 along line V-V. As shown, the embodiment of FIG. 4 is the same as theembodiment of FIG. 1 except for the bump structures. In the embodimentof FIG. 4, each bump structure 100′ is the same as the bump structure100 shown in FIG. 1 except that the conductive layer 108 covers a sameone of the sidewalls 104 facing in the first direction. As such, theconductive sidewall 104 of one bump structure 100 faces a non-conductivesidewall 104 of another bump structure 100.

Because one of the sidewalls 104 of the bump structures 100 facing inthe first direction are non-conductive, short circuits are prevented.Consequently, the present invention provides a bump structure thatremoves barriers on the spacing between solder bumps of semiconductorchips or packages. As such, the present invention allows for smaller andthinner semiconductor devices.

Third Structural Embodiment

FIG. 6 illustrates a semiconductor device having a bump structureaccording to an exemplary embodiment of the present invention, and FIG.7 illustrates a cross-section of the semiconductor device shown in FIG.6 along line VII-VII. As shown, the embodiment of FIG. 6 is the same asthe embodiment of FIG. 1 except for the bump structures. The embodimentof FIG. 6 includes two alternating types of bump structures. The firsttype of bump structures 100 are the same as the bump structure 100 shownin FIG. 1. The second type of bump structures 100″ are the same as thebump structure 100 shown in FIG. 1 except that the conductive layer 108covers both of the sidewalls 104 facing in the first direction. However,because the two types of bump structures alternate along the firstdirection of the substrate 200, a conductive sidewall 104 of the secondtype of bump structure 100″ faces a non-conductive sidewall 104 of thefirst type of bump structure 100. As a result, short circuits areprevented. Consequently, the present invention provides a bump structurethat removes barriers on the spacing between solder bumps ofsemiconductor chips or packages. As such, the present invention allowsfor smaller and thinner semiconductor devices.

Fourth Structural Embodiment

FIG. 8 illustrates a semiconductor device having a bump structureaccording to an exemplary embodiment of the present invention. As shown,the bump structure in FIG. 8 is the same as the bump structure shown inFIG. 1, except that the successively arrayed bump structures aredisposed offset from one another in the second direction. Morespecifically, the bump structures 100 are divided into two groups. Thebump structures 100-1 in the first group have shorter conductive lines110 than the bump structures 100-2 in the second group, and bumpsstructures 100-1 of the first group alternate with bump structures 100-2of the second group in the first direction.

As will be appreciated, offsetting the bump structures 100 as shown inFIG. 8 further assists in preventing possible short circuits. Becausesuccessive bump structures 100 are not aligned, a short circuit is lesslikely to occur, and because the gap between aligned bump structures islarge (e.g., greater than 20 um), a short circuit is less likely tooccur.

While the embodiment of FIG. 8 has been shown and described using thebump structures 100 of FIG. 1, it will be appreciated that thisembodiment may be used in conjunction with the bump structures of any ofthe previously described embodiments.

Furthermore, while two groups o,f aligned bump structures have beenillustrated, it will be appreciated that more than two groups of bumpstructures, each offset from the other, may be formed. FIG. 9illustrates a top down view of a semiconductor device having threegroups of bump structures 100.

Method Embodiment

Next, a method of fabricating a semiconductor device having a bumpstructure according to the present invention will be described. For thepurposes of example only, the method will be described with respect tothe fabrication of the bump structure 100 illustrated in FIG. 1. Themethod will be described with respect to FIGS. 10A-15B where FIGS. 10A,11A, 12, 13A, 14 and 15A represent cross-sectional views of thesubstrate during the fabrication process, and FIGS. 10B, 11B, 13B and15B represent top down views of the substrate during the fabricationprocess.

As shown in FIGS. 10A and 10B, the process begins with a substrate 200having chip pads 204 formed thereon. For the purposes of clarity, only asingle chip pad has been shown. Also, for clarity, the devices,circuits, etc. to which the chip pad 204 is electrically connected havenot been shown. A first passivation layer 202 is formed over thesubstrate 200 and then patterned to expose a portion 225 of the chip pad204. The first passivation layer 202 may be SiN, SiO2, or SiN+SiO2, andmay be formed by chemical vapor deposition (CVD).

Next, a dielectric layer such as polyimide, BCB (Benzo Cyclo Butane),PBO (polybenzo oxazole), photosensitive resin, etc. is formed over thesubstrates; for example, by spin coating. The dielectric layer may beformed to a thickness of 2-30 um. Then, the dielectric layer ispatterned using a mask to form non-conductive bumps 102 as shown inFIGS. 11A and 11B. The bumps 102 will have a height of 2-30 um, may havea width of 10-50 um and a length of 50-200 um. In one exampleembodiment, the width is 20 um and the length is 100 um.

As shown in FIG. 12, a first metal layer 140 is formed over thesubstrate 200. The first metal layer 140 may have a thickness of 0.05-1um. The first metal layer 140 may be formed of any metal having goodadhesive properties and low electrical resistance such as TiW, Cr, Cu,Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, NiV/Cu, etc. Also the firstmetal layer 140 may be formed by a pressure vapor deposition (PVD)process, electro or electroless plating, etc.

Next, as shown in FIGS. 13A and 13B, a photoresist pattern 150 is formedover the substrate 200. The photoresist pattern 150 forms a mask asshown in FIG. 13B. Using this mask, a second metal layer 160 is formedover portions of the substrate 200 exposed by the mask. The first andsecond metal layers 140 and 160 form the conductive layer 108 and theconductive line 110.

The second metal layer 160 may be formed to a thickness of 1-10 um. Inone example embodiment, the combined thickness of the first and secondmetal layers 140 and 160 is less than 10 um. The second metal layer 160may be formed of Au, Ni, Cu, Pd, Ag, etc., or multiple layers of thesemetals by electro plating, for example.

Afterwards, the photoresist pattern 150 is removed as shown in FIG. 14leaving the bump structure 100 electrically connected to the pad 204. Asecond passivation layer 180 may then be formed over the substrate 200and patterned to expose the bump structures 100 as shown in FIGS. 15Aand 15B. The second passivation layer may be polyimide, BCB, PBO,photosensitive resin etc., and may be applied by a spin coating process.

The bump structures and method of fabrication described above may beapplied to any technique in which bumps are used such as tape carrierpackage (TCP), chip on film (COF), and chip on glass (COG). Also, thebump structures and method of fabrication described above may be appliedto the manufacture of any semiconductor chip or package (e.g., a liquidcrystal display (LCD) driver integrated circuit (IC) package).

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the invention, and all such modifications are intended tobe included within the scope of the invention.

1. A semiconductor device, comprising: a plurality of bump structuresarrayed along a substrate in a first direction, each bump structurehaving a width in the first direction greater than a pitch gap betweensuccessively arrayed bump structures, and at least one bump structurehaving a sidewall facing in the first direction that is non-conductive.2. The semiconductor device of claim 1, wherein each bump structure hasat least one non-conductive sidewall facing in the first direction. 3.The semiconductor device of claim 2, wherein each bump structure has twooppositely facing non-conductive sidewalls facing in the firstdirection.
 4. The semiconductor device of claim 3, wherein each bumpstructure includes a conductive layer disposed over a top surface of thebump structure and disposed over at least one sidewall of the bumpstructure that faces in a second direction, the conductive layerextending from the sidewall facing in the second direction over aportion of the substrate.
 5. The semiconductor device of claim 4,wherein each conductive layer is electrically connected to an associatedpad on the substrate, the associated pad being disposed away from theassociated bump structure.
 6. The semiconductor device of claim 4,wherein each conductive layer includes at least a lower metal layer andan upper metal layer.
 7. The semiconductor device of claim 4, whereinsuccessively arrayed bump structures are disposed offset from oneanother in the second direction along the substrate.
 8. Thesemiconductor device of claim 7, wherein the second direction issubstantially perpendicular to the first direction.
 9. The semiconductordevice of claim 2, wherein each bump structure has one non-conductivesidewall facing in the first direction and one conductive sidewallfacing in the first direction such that the conductive sidewall does notface the conductive sidewall of another bump structure.
 10. Thesemiconductor device of claim 9, wherein each bump structure includes aconductive layer disposed over a top surface of the bump structure anddisposed over at least one sidewall of the bump structure that faces ina second direction, the conductive layer extending from the sidewallfacing in the second direction over a portion of the substrate.
 11. Thesemiconductor device of claim 10, wherein each conductive layer iselectrically connected to an associated pad on the substrate, theassociated pad being disposed away from the associated bump structure.12. The semiconductor device of claim 10, wherein each conductive layerincludes at least a lower metal layer and an upper metal layer.
 13. Thesemiconductor device of claim 10, wherein successively arrayed bumpstructures are disposed offset from one another in the second directionalong the substrate.
 14. The semiconductor device of claim 13, whereinthe second direction is substantially perpendicular to the firstdirection.
 15. The semiconductor device of claim 1, Wherein the array ofbump structures alternate from a first type to a second type, the bumpstructure of the first type has two oppositely facing non-conductivesidewalls that face in the first direction, and the bump structure ofthe second type has each sidewall being conductive.
 16. Thesemiconductor device of claim 15, wherein each bump structure includes aconductive layer disposed over a top surface of the bump structure anddisposed over at least one sidewall of the bump structure that faces ina second direction, the conductive layer extending from the sidewallfacing in the second direction over a portion of the substrate.
 17. Thesemiconductor device of claim 16, wherein each conductive layer iselectrically connected to an associated pad on the substrate, theassociated pad being disposed away from the associated bump structure.18. The semiconductor device of claim 16, wherein each conductive layerincludes at least a lower metal layer and an upper metal layer.
 19. Thesemiconductor device of claim 16, wherein successively arrayed bumpstructures are disposed offset from one another in the second directionalong the substrate.
 20. The semiconductor device of claim 19, whereinthe second direction is substantially perpendicular to the firstdirection.
 21. The semiconductor device of claim 1, wherein each bumpstructure includes a conductive layer disposed over a top surface of thebump structure and disposed over at least one sidewall of the bumpstructure that faces in a second direction, the conductive layerextending from the sidewall facing in the second direction over aportion of the substrate.
 22. The semiconductor device of claim 21,wherein each conductive layer is electrically connected to an associatedpad on the substrate, the associated pad being disposed away from theassociated bump structure.
 23. The semiconductor device of claim 21,wherein each conductive layer includes at least a lower metal layer andan upper metal layer.
 24. The semiconductor device of claim 23, whereinthe lower metal layer has a thickness of 0.05 to 1 um, and the uppermetal layer has a thickness of 1 to 10 um.
 25. The semiconductor deviceof claim 23, wherein the lower metal layer includes at least one of TiW,Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, and NiV/Cu, and theupper metal layer includes at least one of Au, Ni, Cu, Pd, Ag, and Pt.26. The semiconductor device of claim 1, wherein successively arrayedbump structures are disposed offset from one another in a seconddirection along the substrate.
 27. The semiconductor device of claim 26,wherein the second direction is substantially perpendicular to the firstdirection.
 28. The semiconductor device of claim 1, wherein the bumpstructures have a width of 10 to 50 um.
 29. The semiconductor device ofclaim 1, wherein each bump structure includes a non-conductive bump anda conductive material disposed on at least a top surface of thenon-conductive bump.
 30. The semiconductor device of claim 29, whereineach bump has a height of 2-30 um.
 31. The semiconductor device of claim29, wherein each bump structure includes the conductive materialdisposed on two oppositely facing sidewalls that face in the seconddirection, and the conductive material extends over the substrate fromeach of the two oppositely facing sidewalls.
 32. The semiconductordevice of claim 29, wherein each bump includes one of a polyimide, benzocyclo butane, poly benzoxazole, and photosensitive resin.
 33. Asemiconductor device, comprising: a plurality of bumps arrayed along asubstrate in a first direction; a plurality of conductive lines formedin a second direction, each conductive line associated with one of thebumps, each conductive line disposed over a top surface of theassociated bump and disposed over two oppositely facing sidewalls of thebump that face in the second direction, and each conductive lineextending over the substrate from each of the two oppositely facingsidewalls.
 34. A semiconductor device, comprising: a plurality of bumpsarrayed along a substrate in a first direction, each bump having a widthin the first direction greater than a pitch gap between successivelyarrayed bumps; and a plurality of conductive lines formed in a seconddirection, each conductive line associated with one of the bumps, eachconductive line disposed over a top surface of the associated bump anddisposed over a sidewall of the associated bump that faces in the seconddirection, and each conductive line extending over the substrate fromthe sidewall facing in the second direction.
 35. A method of forming asemiconductor device, comprising: forming a plurality of bump structuresarrayed along a substrate in a first direction, each bump structurehaving a width in the first direction greater than a pitch gap betweensuccessively arrayed bump structures, and at least one bump structurehaving a sidewall facing in the first direction that is non-conductive.36. The method of claim 35, wherein the forming step comprises: forminga plurality of bumps arrayed along the substrate in the first direction;and forming a conductive line associated with each bump in a seconddirection, each conductive line disposed over a top surface of theassociated bump and disposed over a sidewall of the associated bump thatfaces in the second direction, and each conductive line extending overthe substrate from the sidewall facing in the second direction.
 37. Themethod of claim 35, wherein the forming a plurality of bumps stepcomprises: spin coating a bump material on the substrate; and patterningthe bump material to form the plurality of bumps.
 38. The method ofclaim 37, wherein each bump includes one of a polyimide, benzo cyclobutane, poly benzoxazole, and photosensitive resin.
 39. The method ofclaim 37, wherein the patterning step forms the plurality of bumps suchthat each bump has a width of 10 to 50 um.
 40. The method of claim 37,wherein the patterning step forms the plurality of bumps such that eachbump has a height of 2-30 um.
 41. The method of claim 35, wherein eachconductive line includes at least a lower metal layer and an upper metallayer.
 42. The method of claim 41, wherein the lower metal layer has athickness of 0.05 to 1 um, and the upper metal layer has a thickness of1 to 10 um.
 43. The method of claim 41, wherein the lower metal layerincludes at least one of TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu,TiW/Au, and NiV/Cu, and the upper metal layer includes at least one ofAu, Ni, Cu, Pd, Ag, and Pt.
 44. The method of claim 41, wherein theforming a conductive line step comprises: forming the lower metal layer;and electroplating the lower metal layer with an upper metal layermaterial to form the upper metal layer.
 45. The semiconductor device ofclaim 35, wherein each bump structure has at least one non-conductivesidewall facing in the first direction.
 46. The semiconductor device ofclaim 35, wherein each bump structure has two oppositely facingnon-conductive sidewalls facing in the first direction.
 47. Thesemiconductor device of claim 35, wherein each bump structure has onenon-conductive sidewall facing in the first direction and one conductivesidewall facing in the first direction such that the conductive sidewalldoes not face the conductive sidewall of another bump structure.
 48. Thesemiconductor device of claim 35, wherein the array of bump structuresalternate from a first type to a second type, the bump structure of thefirst type has two oppositely facing non-conductive sidewalls that facein the first direction, and the bump structure of the second type haseach sidewall being conductive.
 49. A method of forming a semiconductordevice, comprising: forming a plurality of bumps arrayed along asubstrate in a first direction, each bump having a width in the firstdirection greater than a pitch gap between successively arrayed bumps;and forming a plurality of conductive lines formed in a seconddirection, each conductive line associated with one of the bumps, eachconductive line disposed over a top surface of the associated bump anddisposed over a sidewall of the associated bump that faces in the seconddirection, and each conductive line extending over the substrate fromthe sidewall facing in the second direction.